Time to digital converter with error protection

ABSTRACT

Time to digital converters (TDCs) with high resolution are disclosed. The TDC includes a first time to digital converting module, a selection and time amplifying module, a second time to digital converting module and a decoder, and is applied in estimating a time difference between a first signal and a second signal. As the delay time of the delay units of the time to digital converting modules is the unit of the time difference measurement, the first and second time to digital converting modules are responsible for the integral portion and the fractional portion of the estimated time difference, respectively. Moreover, by introducing the normalization process, the linearity of the converting characteristic of the TDC can be improved; by adding an error detection circuit to the TDC, the possible metastable problem can be prevented.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to co-pending U.S. utility application Ser.No. 12/235,624, filed on Sep. 23, 2008, entitled “Error ProtectionMethod, TDC module, CTDC Module, All-Digital Phase-Locked Loop, andCalibration Method thereof” and claiming the priority of U.S.Provisional Applications No. 60/980,172 filed on Oct. 16, 2007 and60/980,461 filed on Oct. 17, 2007, the entirety of which is incorporatedherein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to time to digital converters (TDCs), andin particular relates to high resolution TDCs.

2. Description of the Related Art

FIG. 1A illustrates a conventional time to digital converter (TDC),which estimates the time difference between a first signal A and asecond signal B. The conventional TDC comprises a time to digitalconverting module 102 and a decoder 104. The time to digital convertingmodule 102 comprises a plurality of delay units DU₁˜DU₄ and aD-Flip-Flops array 106. The first signal A is sequentially delayed bythe delay units DU₁˜DU₄, and a plurality of delayed first signals A₁˜A₄are generated and sent to the D-Flip-Flops array 106. The D-Flip-Flopsarray 106 is triggered by the second signal B to read out the states ofthe delayed first signals A₁˜A₄ (i.e. to read out whether the delayedfirst signals A₁˜A₄ are at the high voltage levels or low voltagelevels). Digital data data_D[0:3], showing the states of A₁˜A₄, are sentto the decoder 104 to be decoded. The output 108 of the decoder 104 isthe estimated time difference between the first and second signals A andB.

FIG. 1B uses waveforms to show the functions of the TDC of FIG. 1A. Eachdelay unit (DU₁, DU₂ . . . or DU₄) delays the input signal by a unitdelay time T. When the second signal B rises from low to high, theD-Flip-Flops array 106 is triggered to read out the states of thedelayed first signals A₁˜A₄. In this case, the digital data data_D[0:3]are [1, 0, 0, 0]. The decoder 104 decodes the digital data [1, 0, 0, 0]as 1, which means that the estimated time difference between the signalsA and B is greater than one unit delay time T and smaller than two unitdelay time 2T. This structure of FIG. 1A limits the estimationresolution to the unit delay time T and is incapable of estimating thefraction part. The output of the decoder 104 is an integer multiple ofunit delay time T.

Since the value of the unit delay time T is mainly dependent on themanufacturing process of the delay units DU₁˜DU₄, it is difficult toimprove the estimation resolution of the conventional TDCs. Thus, novelTDC architectures with higher resolution are called for.

BRIEF SUMMARY OF THE INVENTION

The invention discloses time to digital converters. According to oneembodiment, the time to digital converter comprises a first time todigital converting module, a selection and time-amplifying module, asecond time to digital converting module and a decoder. The first timeto digital converting module delays a first signal to generate aplurality of delayed first signals, and reads out the states of thedelayed first signals according to a second signal. The read-out statesform first digital data. The selection and time-amplifying moduledetermines the first zero bit of the first digital data and then selectsand stretches the corresponding delayed first signal. The stretchedresult is outputted by the selection and time-amplifying module as afirst reference signal. In additional to outputting the first referencesignal, the selection and time-amplifying module further stretches thesecond signal along the time axis and outputs the stretched secondsignal. The second time to digital converting module delays thestretched second signal to generate a plurality of delayed and stretchedsecond signals, and reads out the states of the delayed and stretchedsecond signals according to the first reference signal to generatesecond digital data. The first and second digital data are sent to thedecoder to be decoded for estimating a time difference between the firstand second signals.

A detailed description is given in the following embodiments withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by reading thesubsequent detailed description and examples with references made to theaccompanying drawings, wherein:

FIG. 1A illustrates a conventional TDC;

FIG. 1B shows waveforms to explain the functions of the TDC of FIG. 1A;

FIG. 2A illustrates a TDC of the invention;

FIG. 2B-2D show waveforms to explain the functions of the TDC of FIG.2A;

FIG. 3A illustrates another embodiment of the TDC of the invention;

FIG. 3B shows waveforms to explain the functions of the TDC of FIG. 3A;

FIG. 4 shows waveforms to explain the effect of a metastable problem;and

FIG. 5 illustrates another embodiment of the TDC of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The following description shows the embodiments of carrying out theinvention. This description is made for the purpose of illustrating thegeneral principles of the invention and should not be taken in alimiting sense. The scope of the invention is best determined byreference to the appended claims.

FIG. 2A illustrates an embodiment of the time to digital converter ofthe invention, which estimates a time difference between a first signalA and a second signal B. The time to digital converter comprises a firsttime to digital converting module 202, a selection and time-amplifyingmodule 204, a second time to digital converting module 206 and a decoder208. In this embodiment, the first time to digital converting module 202comprises a plurality of delay units DU₁˜DU₄ and a D-Flip-Flops array210. The delay units DU₁˜DU₄ are coupled in series to delay the firstsignal A to generate a plurality of delayed first signals A₁˜A₄. TheD-Flip-Flops array 210 is triggered by the second signal B to read outthe states of the delayed first signals A₁˜A₄ (e.g. to read out whetherthe delayed first signals A₁˜A₄ are at the high voltage levels or lowvoltage levels when the D-Flip-Flops array 210 is triggered), whereinthe read-out states are shown by first digital data data_D[0:3]. In thisembodiment, the selection and time-amplifying module 204 comprises aplurality of time amplifiers TA₁˜TA₅ and a selection circuit 212. Thetime amplifiers TA₁˜TA₅ stretches (or enlarges the width of) the delayedfirst signals A₁˜A₄ and the second signal B along the time axis,respectively, to generate stretched and delayed first signals SA₁˜SA₄and a stretched second signal SB. FIG. 2B depicts the waveforms of thefirst signal A, the delayed first signals A₁˜A₄ and the stretched anddelayed first signals SA₁˜SA₄. The first signal A is sequentiallydelayed by a time delay T to generates the delayed first signals A₁˜A₄.The delayed first signals A₁˜A₄ are stretched by M times as shown inFIG. 2B. FIG. 2C depicts the waveforms of the second signal B and thestretched second signals SB. As shown in FIG. 2C, after being stretchedby the time amplifier TA₅ the second signal B is stretched to thestretched second signal SB and time width t_(r) is amplified by M times,M t_(r). The selection circuit 212 receives the first digital datadata_D[0:3], finds out the first logic ‘0’ thereof to determine it as afirst zero bit, and selects the corresponding stretched and delayedfirst signal (selected from the delayed and stretched first signals SA₁,SA₂ . . . or SA₄ according to the first zero bit) as a first referencesignal 214. In the second time to digital converting module 206, thestretched second signal SB is delayed and a plurality of delayed andstretched second signals SB₁˜SB₄ are generated. The first referencesignal 214 is sent to the second time to digital converting module 206to trigger the D-Flip-Flops array 216 to read out the states of thedelayed and stretched second signals SB₁˜SB₄. The second digital datadata_F[0:3] representing the read-out states are generated. The decoder208 decodes the first and second digital data data_D[0:3] anddata_F[0:3] to get decoded values D and F. With proper calculations, thedecoder 208 outputs an output digital signal 218 representing theestimated time difference between the first and second signals A and B.

Please note that the number of the delay units DU in the first andsecond time to digital converting modules 202 and 206 and the number ofthe time amplifiers TA in the selection and time-amplifying module 204shown in this embodiment are for illustrative purpose only. The numbersand configurations of the delay units DU and the time amplifiers TA canbe modified according to circuit requirements.

Using the delay time T of the delay units adopted in the time to digitalconverting modules 202 and 206 as a unit of estimating the timedifference between the first and the second signals A and B, the decodedvalues D and F relate to the integral and fractional portions of theestimated time difference, respectively. When the time amplifiersTA₁˜TA₅ stretch their input signals along the time axis by M times, thedecoder 208 executes a calculation of DT+(1−F/M)T to estimate the timedifference between the first and second signals A and B.

For further explain the operation of the TDC shown in FIG. 2A, the firstand second signals A and B of FIG. 1B are taken as an example. The firsttime to digital converting module 202 works similar to the time todigital converting module 102 and outputs [1,0,0,0] as the first digitaldata data_D[0:3]. The selection circuit 212 identifies that the firstlogic ‘0’ in data_D[0:3] is located at the second bit, and thendetermines that the second bit is the first zero bit of data_D[0:3]. Inother words, the transition of the second signal B occurs between thetransition of the delayed first signal A₁ and the transition of thedelayed first signal A₂. Based on the identifying result, the selectioncircuit 212 selects the stretched and delayed first signal SA₂ as thefirst reference signal 214. FIG. 2D shows the waveforms of the stretchedsecond signal SB, the delayed and stretched second signals SB₁˜SB₄, andthe first reference signal 214 (SA₂). The first reference signal 214(SA₂) triggers the D-Flip-Flops array 216 to read out the states of thedelayed and stretched second signals SB₁˜SB₄ to get the second digitaldata data_F[0:3]. In the case shown in the FIG. 2D,data_F[0:3]=[1,0,0,0].

The decoder 208 decodes the first digital data data_D[0:3] (=[1,0,0,0])and the second digital data data_F[0:3] (=[1,0,0,0]) as 1 (D=1) and 1(F=1), respectively, and then performs a calculation of DT+(1−F/M)T. Thecalculated result is 1 T+(1−½)T=1.5 T. Compared with the conventionalTDC shown in FIG. 1A, the TDC shown in FIG. 2A not only estimates theintegral portion of the time difference between the first and secondsignals A and B, further estimates the fractional portion thereof. Theinvention provides TDCs with higher resolution.

FIG. 3A illustrates another embodiment of the invention. Compared withthe embodiment of FIG. 2A, the selection and time-amplifying module andthe second time to digital converting module are replaced by modules 312and 314, respectively. In the selection and time-amplifying module 312,the selection circuit 302 further selects another signal from thestretched and delayed first signals (SA₁-SA₄) to output as a secondreference signal 304. Generally, the second reference signal 304 followsthe first reference signal 214 and leads the other stretched and delayedfirst signals that lags the first reference signal 214. In addition tothe first reference signal 214, the D-Flip-Flops array 306 is furthertrigger by the second reference signal 304 to read out the states of thestretched and delayed second signals SB₁˜SB₄. The read-out states arethe third digital data data_N[0:3]. Compared to the decoder 208, thedecoder 308 further decodes the third digital data data_N[0:3] to get adecoded value N. The difference between the decoded values N and F is(N−F) and is used in normalizing the decoded value F. With propercalculations, the decoder 308 outputs the estimated time differencebetween the first and second signals A and B by the output signal 310.

Using the delay time T of the delay units adopted in the time to digitalconverting modules 202 and 314 as a unit of estimating the timedifference between the first and the second signals A and B, the decodedvalue D relates to the integral portion of the estimated timedifference, and the decoded values F and N relate to the fractionalportion of the estimated time difference. To estimate the timedifference between the first and second signals A and B, the decoder 308executes a calculation of DT+(1−F/(N−F))T, or DT+(1−F/Avg(N−F))T. Avg(.)represents an average operation, which accumulates the calculated (N−F)and averages them.

Referring to the aforementioned case, the stretched and delayed firstsignal that follows the first reference signal (SA₂) is SA₃. Theselection circuit 302 therefore selects SA₃ as the second referencesignal 304. Compared to FIG. 2B, FIG. 3B further shows the waveform ofSA₃. The second reference signal (SA₃) triggers the D-Flip-Flops array306 to read out the states of the delayed and stretched second signalsSB₁˜SB₄ to get the third digital data data_N[0:3]. As shown in thefigure, data_N[0:3]=[1,1,1,0].

In addition to getting the decoded values D=1 and F=1, the decoder 308further decodes the third digital data data_N[0:3] as 3 (N=3), and thenperforms a calculation of DT+(1−F/(N−F))T. The calculated result is 1T+(1−1/(3−1))T=1.5 T. Compared with the conventional TDC shown in FIG.1A, the TDC shown in FIG. 3A not only estimates the integral portion ofthe time difference between the first and second signals A and B,further estimates the fractional portion thereof. This exemplaryembodiment provides TDCs with higher resolution.

In some cases, because of metastable, the D-Flip-Flops array 210 may notcorrectly identify the states of the delayed first signals A₁-A₄ andoutput incorrect first digital data data_D[0:3]. In the case that thefirst and second signals A and B are those shown in FIG. 1B, resultingin close waveforms of the second signal B and the delay first signal A₁,the metastable may cause the D-FlipFlops array 210 to output incorrectdigital data [0,0,0,0] instead of the correct digital data [1,0,0,0].The incorrect digital data causes the selection circuit 302 to outputincorrect reference signals 214 and 304 to trigger the D-Flip-Flopsarray 306 of the second time to the digital converting module 314. Inthe case that the incorrect first digital data data_D[0:3] are[0,0,0,0], the selection circuit 302 wrongly selects SA₁ and SA₂ as thefirst and second reference signals 214 and 304. FIG. 4 shows thewaveforms of the stretched second signal SB, the stretched and delayedsecond signals SB₁-SB₄, and the wrongly selected reference signals SA₁and SA₂. As shown in the figure, the second digital datadata_F[0:3]=[0,0,0,0] and the third digital data data_N[0:3]=[1,0,0,0].The decoder 308 decodes the digital data data_D[0:3], data_F[0:3] anddata_N[0:3] and gets the decoded values D=0, F=0 and N=1, respectively,and then executes the calculation, DT+(1−F/(N−F))T, orDT+(1−F/Avg(N−F))T, to calculate the time difference between first andsecond signal A and B. The calculated result is 1 T. Compared with theaforementioned normal result, 1.5 T, the operation of the TDC isaffected by the metastable problem.

As such, to overcome the metastable problem, the invention furtherdiscloses TDCs with error protection. FIG. 5 shows an embodiment of theTDC with error protection. Compared with FIG. 3A, the TDC of FIG. 5further comprises an error detector 502, which detects the phases of thefirst reference signal 214 and the stretched second signal SB. As shownin FIG. 4, when the metastable occurs, the incorrect first referencesignal (SA₁) leads the stretched second signal SB, which results in zeroF[0:3]. Note that in a normal operation without metastable, the firstreference signal 214 must lag the stretched second signal SB. The errordetection 502 outputs an error protection enable signal 504 to thedecoder 506 when detecting that the first reference signal 214 leads thestretched second signal SB. When receiving the error protection enablesignal 504, the decoder 506 executes a calculation ofDT+(1−N/avg_pre)T+1 T to replace the original calculationDT+(1−F/(N−F))T or DT+(1−F/Avg(N−F))T. avg_pre represents the previousvalue of Avg(N−F). The current value of (N−F) is abandoned.

Referring to the case shown in FIG. 4, the error detector 502 detectsthat the first reference signal (SA₁) is leading the stretched secondsignal SB and then outputs the error protection enable signal 504 toenable the decoder 506 to perform a calculation of DT+(1−N/avg_pre)T+1T. In the case that avg_pre is 2, the calculated result is 0 T+(1−½)T+1T=1.5 T since the decoded values D=0 and N=1. Thus, solving thematastable problem.

The decoders of the invention may realize the aforementionedcalculations by software or hardware.

The structures of the selection and time-amplifying modules 204 and 312are not used to limit the scope of the invention, and may be replaced byother circuits capable of outputting the reference signals (such as thesignal 214 or signals 214 and 304) and the stretched second signal SB.In some embodiments, the selection circuit may be placed prior to thetiming amplifiers TA₁˜TA₄ to first select from the delayed first signalsA₁˜A₄, and then stretch the selected signal along the time axis.

The structures of the time to digital converting modules 202 is not usedto limit the scope of the invention, and other circuits capable ofproducing a plurality of delayed first signals and outputting a firstdigital data representing the time difference between the first andsecond signals, can be applied to replace the module 202. Furthermore,the second time to digital converting modules 206 and 314 can bereplaced by any circuit with the same functions.

To conclude, the first time to digital converting module 202 may beregarded as a coarse converter, while the second time to digitalconverting module 206 (or 314) may be regarded as a fine converter. Forexample, the first time to digital converting module 202 compares atleast a first signal A and a second signal B to generate first digitaldata data_D[0:3] representing a first portion (e.g. the integer part) ofthe phase/time difference between the first and second signals; theselection and time-amplifying module 204 (or 312) stretches (ormagnifies) a second portion (e.g. the fractional part) of the phase/timedifference between the first and second signals A and B to a degree thatthe second time to digital converting module 206 (or 314) can process;and the second time to digital converting module 206 (or 314) thencompares the stretched second portion 214 with at least one stretchedsignal (SB₁˜SB₄ in above embodiment) corresponding to at least one ofthe first signal A and the second signal B to generate second digitaldata data_F[0:3] representing the second portion of the differencebetween the first and second signals. In this way, the resolution of theTDC can be improved. Moreover, by introducing the normalization process,the linearity of the converting characteristic of the TDC can beimproved; by adding the error detection circuit 502, the possiblemetastable problem can be prevented.

Moreover, when the time to digital converters of above embodiments areimplemented in a phase lock loop (PLL) circuit, the high resolutionproperty of the time to digital converter can benefit the PLL to havesmall phase noise.

While the invention has been described by way of example and in terms ofthe preferred embodiments, it is to be understood that the invention isnot limited to the disclosed embodiments. To the contrary, it isintended to cover various modifications and similar arrangements (aswould be apparent to those skilled in the art). Therefore, the scope ofthe appended claims should be accorded the broadest interpretation so asto encompass all such modifications and similar arrangements.

1. A time to digital converter, comprising: a first time to digitalconverting module, for delaying a first signal to generate a pluralityof delayed first signals and reading out states of the delayed firstsignals according to a second signal to generate first digital data; aselection and time-amplifying module, for selecting a first specificdelayed first signal from the plurality of delayed first signals,stretching the first specific delayed first signal along the time axisto generate a first reference signal, and stretching the second signalalong the time axis; a second time to digital converting module, fordelaying the stretched second signal to generate a plurality of delayedand stretched second signals, and reading out states of the delayed andstretched second signals according to the first reference signal togenerate second digital data; and a decoder, for decoding at least thefirst and second digital data to generate an estimation of a timedifference between the first and second signals.
 2. The time to digitalconverter as claimed in claim 1, wherein the selection andtime-amplifying module further finds out a first zero bit in the firstdigital data, and selects the first specific delayed first signalaccording to the first zero bit.
 3. The time to digital converter asclaimed in claim 1, wherein the selection and time-amplifying modulefurther selects and stretches a second specific delayed first signalfrom the plurality of delayed first signals to generate a secondreference signal, and the second specific delayed first signal lags thefirst specific delayed signal by a delay time.
 4. The time to digitalconverter as claimed in claim 3, wherein the second time to digitalconverting module further reads out states of the delayed and stretchedsecond signals according to the second reference signal to generatethird digital data.
 5. The time to digital converter as claimed in claim4, wherein the decoder further decodes the third digital data andgenerates the estimation of the time difference between the first andsecond signals by performing a first calculation on the decoded first,second and third digital data.
 6. The time to digital converter asclaimed in claim 5, further comprising an error detector, for detectingphases of the first reference signal and the stretched second signal andoutputting an error protection enable signal to the decoder when thestretched second signal lags the first reference signal.
 7. The time todigital converter as claimed in claim 6, wherein the decoder is switchedto perform a second calculation to generate the estimation whenreceiving the error protection enable signal.
 8. The time to digitalconverter as claimed in claim 7, wherein the second calculation utilizesprevious decoded second digital data and previous decoded third datarather than the decoded second digital data and decoded third data togenerate the estimation.
 9. A time to digital converter, comprising: afirst time to digital converting module, for delaying a first signal togenerate a plurality of delayed first signals, and reading out states ofthe delayed first signals according to a second signal to generate firstdigital data; a selection and time-amplifying module, for stretching thedelayed first signals and the second signal along a time axis togenerate a plurality of stretched and delayed first signals and astretched second signal, and selecting one stretched and delayed firstsignal from the plurality of stretched and delayed first signals as afirst reference signal according to the first digital data; a secondtime to digital converting module, for delaying the stretched secondsignal to generate a plurality of delayed and stretched second signals,and reading out states of the delayed and stretched second signalsaccording to the first reference signal to generate second digital data;and a decoder, for decoding at least the first and second digital datato generate an estimation of a time difference between the first andsecond signals.
 10. The time to digital converter as claimed in claim 9,wherein the first reference signal lags the stretched second signal andleads the other stretched and delayed first signals that lags thestretched second signal.
 11. The time to digital converter as claimed inclaim 9, wherein the selection and time-amplifying module furtherselects another stretched and delayed first signal from the plurality ofstretched and delayed first signals as a second reference signal,wherein the second reference signal lags the first reference signal andleads the other stretched and delayed first signals that lags the firstreference signal.
 12. The time to digital converter as claimed in claim11, wherein the second time to digital converting module further readsout states of the delayed and stretched second signals according to thesecond reference signal to generate third digital data.
 13. The time todigital converter as claimed in claim 12, wherein the decoder furtherdecodes the third digital data, and calculates the difference betweenthe decoded second and third digital data to normalize the decodedsecond digital data.
 14. A time to digital converter, comprising: afirst time to digital converting module, for comparing at least a firstsignal and a second signal to generate first digital data representing afirst portion of a difference between the first and second signals; atime-amplifying module, for stretching a second portion of thedifference between the first and second signals to generate a stretchedsecond portion; a second time to digital converting module, forcomparing the stretched second portion with at least one stretchedsignal corresponding to at least one of the first signal and the secondsignal to generate second digital data representing the second portionof the difference between the first and second signals; and a decoder,for decoding at least the first and second digital data to generate anestimation of a time difference between the first and second signals.15. The time to digital converter as claimed in claim 14, wherein thefirst portion corresponds to integer part of the difference, and thesecond portion corresponds to fractional part of the difference.
 16. Thetime to digital converter as claimed in claim 14, further comprising anerror detector, for detecting error of the time-amplifying module andoutputting an error protection enable signal to the decoder when theerror is detected.
 17. The time to digital converter as claimed in claim16, wherein the decoder decodes the first and second digital data byperforming a first calculation scheme when the error protection enablesignal is not received, and is switched to perform a second calculationscheme different from the first calculation scheme when receiving theerror protection enable signal.
 18. The time to digital converter asclaimed in claim 14, wherein the decoder further normalizes the seconddigital data before generating the estimation of the time differencebetween the first and second signals.